A semiconductor integrated circuit having less floating capacity, obtains higher performance by isolating circuit elements with dielectric zones. In the case of forming transistors in a thin film silicon layer formed on an insulating film (hereinafter referred to as SOI layer), a so-called MESA isolation method is conventionally employed. In the MESA isolation method, the SOI layer between circuit elements are removed by is etching to isolate the circuits elements, and transistors are formed in each completely island-like semiconductor layer. The MESA isolation method has many advantages, including freedom from latch-up with adjacent transistors.
FIGS. 30 to 44 are schematic views of a conventional SOI MOSFET. Specifically, FIG. 30 is a plan view showing a structure of conventional SOI MOSFET. FIGS. 31 to 44 are schematic views showing a manufacturing process of the transistor, and in which FIGS. 31 to 37 are sectional views taken along the line 31-37 of FIG. 30, and show the steps of the manufacturing process. FIGS. 38 to 44 are sectional views taken along the line 38-40 of FIG. 30, and show the steps of the manufacturing process. FIG. 37 shows a sectional structure taken along the line 31-37 of a plan structure of FIG. 30, and FIG. 44 shows a sectional structure taken along the line 38-40 of FIG. 30.
The SOI MOSFET is isolated by the MESA isolation method, and as illustrated in the drawings, a silicon-buried oxide film 2 is formed on a silicon substrate 1 to serve as an insulating substrate. A thin film silicon semiconductor layer 3 is further formed thereon, and divided into element forming regions 4. A silicon oxide film 5 is filled-in or buried up to the same level as the element forming regions 4 so as to surround each region 4.
A FET is formed in each of the element forming regions 4, and the FET has a gate oxide film 7, a polysilicon layer 8 serving as a gate electrode, an insulating film 9 on the sides of the gate electrode, and a source/drain region 10. The gate electrode 8 is made of a polysilicon containing a phosphorus of not less than 1.times.10.sup.20 /cm.sup.3 in concentration. The insulating film 9 surrounds the gate insulating film 7 and the gate 8. The semiconductor device further comprises an interlayer oxide film 11 and metal leads 12.
A manufacturing process of the SOI MOSFET is hereinafter described with reference to FIGS. 31 to 44. First, as illustrated in FIGS. 31 and 38, the surface of the SOI substrate 14 comprising the silicon substrate 1, buried oxide film 2 and SOI layer 3 are subject to oxidation up to 100 to 200 .ANG. in film thickness, forming oxide film 15. Then, a resist 18 is formed, and part of the SOI layer 3 and overlapping oxide film 15 are removed by dry etching, whereby the element forming regions (active regions) 4 are formed. The isolation method called MESA isolation thus cuts electrical connection between adjacent transistors by removing part of the SOI. Then, channel doping is performed to establish a threshold voltage respectively for the NMOS FET and the PMOS FET, though not illustrated. A resist is formed only on the PMOS region, and boron ions of 1 to 6.times.10.sup.12 /cm.sup.2 are implanted at 20 KeV into the NMOS region. This is the channel doping for the NMOSFET. Further, after removing the resist of the PMOS region, a resist is formed again only on the NMOS region, and phosphorus ions of 1 to 3.times.10.sup.11 /cm.sup.2 are implanted at 30 KeV into the PMOS region. This is the channel doping for the PMOSFET.
Then, as illustrated in FIGS. 32 and 39, an oxide film 21 of 100 to 500 nm is deposited by chemical vapor deposition (CVD). Subsequently, as illustrated in FIGS. 33 and 40, the deposited oxide film 21 is etched (etching back) with strong anisotropy. As illustrated in these drawings, the oxide film 5 is left in different shapes depending on the space or distance between element forming regions 4 (transistor forming regions). As a result, transistor characteristics of each transistor are not always uniform, but different depending on the pattern of the transistor forming regions 4. More specifically, if the distance between the adjacent transistor forming regions 4 is large, the oxide film 5 is shaped like a spacer. On the other hand, if the distance between the adjacent transistor forming regions 4 is small, the oxide film 5 is in a buried or filled form.
Then, as illustrated in FIGS. 34 and 41, a gate insulating film 7 and a polysilicon 8 are formed. The gate insulating film 7 is 100 .ANG. in thickness, and the polysilicon (poly-Si) 8 contains phosphorus of not less than 1.times.10.sup.20 /cm.sup.3 in concentration, and is 2000 .ANG. in film thickness.
After forming the polysilicon 8 into a pattern of gate electrode leads, a resist is formed only on the PMOS region, and phosphorus ions of 1 to 3.times.10.sup.13 /cm.sup.2 are implanted at 40 KeV into the NMOS region, though not illustrated. This is the LDD doping for the NMOS FET. Next, a resist is formed only on the NMOS region, and boron ions of 1 to 3.times.10.sup.13 /cm.sup.2 are implanted at 20 KeV into the PMOS region, though not illustrated. This is the LDD doping for the PMOS FET.
After removing the resist on the NMOS region, an insulating film 9 is formed only on the side surface of the gate electrode 8 through the step illustrated in FIGS. 35 and 42. In this process, an insulating film is first deposited and then etched with strong anisotropy, whereby the insulating film 9 may be left self-conformably only on the side surface of the gate electrode 8. Then, a resist is formed only on the PMOS region, and phosphorus ions of 4 to 6.times.10.sup.13 /cm.sup.2 are implanted at 40 KeV into the NMOS region as illustrated in FIGS. 35 and 42. This is the source/drain doping for the NMOS FET. Next, a resist is formed only on the NMOS region, and boron ions of 4 to 6.times.10.sup.13 /cm.sup.2 are implanted at 20 KeV into the PMOS region, though not illustrated. This is the source/drain doping for the PMOS FET.
Then, as illustrated in FIGS. 36 and 43, the interlayer insulating film 11 of 7000 .ANG. in thickness is formed. A resist 18a is further applied thereon, in which contact holes are formed to communicate to the gate electrode 8 and source/drain 10. Subsequently, as illustrated in FIGS. 37 and 44, a metal layer mainly composed of aluminum is formed by sputtering, and aluminum leads 12 are patterned. Thus, a SOI MOSFET is formed.
In the step illustrated above in FIGS. 33 and 40 of the conventional manufacturing process, it is certain that desirable transistor characteristics are obtained, when the oxide film 5 is filled between two adjacent transistor forming regions 4. When the oxide film 5 is shaped like a spacer, there is a disadvantage of a hump occurring in the subthreshold characteristic, resulting in an increase in leakage current.
FIG. 45 is a schematic view for explaining the cause of such a disadvantage. The spacers 5 are over-etched by etching back the oxide film 11, and the spacers 5 are further etched by wet treatment for removing the oxide film prior to the gate formation, whereby an upper corner portion (parasitic MOS) of each SOI element forming region 4 becomes exposed. As a result, the gate electric field is concentrated at the corner portions, and the threshold voltage is lowered, eventually resulting in occurrence of hump in the subthreshold characteristic.
Notwithstanding, the etching back of the oxide film 11 performed in the steps illustrated in FIGS. 32 to 33 and FIGS. 39 to 40 is an essential process. Without the etching back, the characteristics will deteriorate.
FIGS. 46 to 48 are schematic views explaining the mentioned disadvantages. That is, after etching the SOI layer 3 using the resist mask 18 as illustrated in FIG. 46, the resist 18 is removed as illustrated in FIG. 47. Then, at the time of removing the oxide film 15 on the transistor forming region 4 by wet treatment, the buried oxide film 2 is also etched. In the gate forming steps performed later, the gate 8 wraps around the lower corner portions of the transistor forming region 4 as illustrated in FIG. 48. The gate electric field concentration also takes place at the lower corner portion of the transistor forming region 4 in addition to the mentioned disadvantage of the gate electric field concentration at the upper corner portion. As a result, problems arise such as lowering in threshold voltage at the lower corner portion, deterioration in subthreshold characteristic, and increase in drain leak current.
Another conventional manufacturing process is hereinafter described. FIGS. 49 to 51 show a process using chemical mechanical polishing (CMP) in order to prevent oxide films on the edge of the element forming regions from being unevenly shaped depending on pattern density, i.e., whether or not patterns of the element forming regions (active regions) are dense on an SOI substrate. After etching an SOI layer 3 using a resist mask 18 as illustrated in FIG. 49, an oxide film 21 is deposited as illustrated in FIG. 50, and is polished by CMP. In this manner, the SOI layer 3 is utilized as a stopper layer to moderate a surface level difference. Nevertheless, a so-called dishing effect may take place on the oxide film 21 depending on pattern density as illustrated in FIG. 51. Accordingly, oxide film thickness is inevitably reduced at the middle portion of the area where there is a large distance between adjacent transistor forming regions 4, which brings about a level difference and increase in gate capacity. Thus, transistor characteristic is not improved in this conventional manufacturing process, either.
A further conventional manufacturing process is hereinafter described. FIGS. 52 to 55 show a process for providing a dummy pattern on the SOI layer 3 in order to prevent reduction in thickness of the oxide film due to the mentioned dishing. As illustrated in FIG. 52, the SOI layer 3 and the dummy layer 23 (polysilicon or nitride film) are etched using a resist mask, and the oxide film 21 is deposited thereon. Then, as illustrated in FIG. 53, using the dummy layer 23 as an etching stopper, the oxide film 21 is etched by CMP. The dummy layer is then removed as illustrated in FIG. 54. Further, part of the thick oxide film 5 near the edge of the SOI layer 3 is etched by wet treatment as illustrated in FIG. 55, thereby the level difference between the SOI layer 3 and the oxide film 5 is moderated. If any sharp step-like level difference still remains, gates may not be formed by patterning. Then, a gate 8 is formed by patterning. However, the disadvantage of dishing is not overcome by this conventional process.
A further conventional manufacturing process is hereinafter described. FIGS. 56 to 58 show a process in which a dummy pattern of the field oxide is preliminarily provided in the region where dishing may take place. In this process, as illustrated in FIG. 56, a dummy region 24 is provided in addition to the required element forming regions 4 to prevent the mentioned dishing. It is certain that dishing due to CMP may be prevented by this process, but the dummy pattern 24 of the SOI layer 3 still remains after forming the gate oxide film 7 and the gate 8 as illustrated in FIG. 58. As a result, gate capacity is undesirably increased by the existence of such dummy patterns of the SOI layer, and it becomes difficult to obtain a circuit comprised of a SOI MOSFET with low power consumption and high operation speed.
A further conventional manufacturing process is hereinafter described. FIGS. 59 to 61 show a process in which a dummy pattern of the oxide film is provided in a region between adjacent transistor regions in order to solve the same problems as in the foregoing conventional processes. As illustrated in FIG. 59, a resist 18c is formed by an additional mask to form a dummy pattern after etching the SOI layer 3. As illustrated in FIG. 60, the dummy pattern 26 is formed by etching the oxide film 25 deposited on the SOI layer 3 using the mentioned resist 18c as a mask. Then, an oxide film 21 is deposited, and as shown in FIG. 61, surface level difference is moderated by CMP. In this process, it is certain that the problems of dishing and gate capacity increase are solved, but the additional mask 18c must be used to form the dummy pattern 26. Moreover, the mask for dummy patterns may be displaced on the patterned SOI layer 3.
As discussed above, in manufacturing an SOI MOSFET, the MESA isolation process has been developed to eliminate negative effects of parasitic transistor. However, in any of the conventional manufacturing processes, a serious problem exists in that manufacturing of a transistor of desirable characteristics is difficult. Difficulty arises because of surface level difference caused by dishing, and because of an increase in gate capacity which is influenced by pattern density in the transistor forming regions.